PSTSWM Paragon Algorithm COmparison

Performance Studies using

PSTSWM

Intel Paragon Algorithm Comparison

(transpose LT experiments II-A2 )

Date/Person: October 21, 1994 / P. Worley
June 4, 1998 / P. Worley
Platform: Intel Paragon at Sandia National Laboratory (acoma):
     1824 GP nodes (2 50-MHz iPSC/860 processors per node)
Intel Paragon XP/S 150 MP at Oak Ridge National Laboratory:
     1024 MP nodes (3 50-MHz iPSC/860 processors per node)
Environment: SUNMOS 1.6.1
  f77/Paragon Paragon Version ???
Paragon OSF/1 Release 1.0.4 Server 1.4 R1_4_5
  f77/Paragon Paragon Version R5.0.3
Code Version: 3.2
Code Version: 6.3
Compilation Options: if77 -O4 -Mnodepchk -Knoieee -Msafealloc
Math Library: none
Communication Library: SUNMOS
NX
Partition: 4x2, 4x4, or 8x4
Number of Timesteps: 12
Results:

Transpose LT (2) (OSF/NX)
Algorithm Comparison
  T42L1     T21L2     T42L2     T85L2     T85L1     T85L4  
  P=32     P=16     P=8     P=32     P=16     P=8  
  optimal algorithm   logtrans  swtrans  swtrans  swtrans  swtrans  srtrans 
  (generic-min)/min     0.176    0.093    0.005    0.024    0.008    0.007 

Transpose LT (2) (SUNMOS)
Algorithm Comparison
  T42L1     T21L2     T42L2     T85L2     T85L1     T85L4  
  P=32     P=16     P=8     P=32     P=16     P=8  
  optimal algorithm   swtrans  swtrans  swtrans  swtrans  swtrans  swtrans 
  (generic-min)/min     0.296    0.138    0.083    0.032    0.192    0.214 

Transpose LT (2) (combined)
Communication Library Comparisons
  T42L1     T21L2     T42L2     T85L2     T85L1     T85L4  
  P=32     P=16     P=8     P=32     P=16     P=8  
  optimal library   sunmos  sunmos  sunmos  sunmos  sunmos  sunmos 
  (osfnx-min)/min     0.221    0.237    0.293    0.250    0.501    0.535 

DISCUSSION

The Paragon processor grid partitions were chosen to match those used for the October, 1994 SUNMOS data.
Patrick H. Worley / ( worleyph@ornl.gov)
Last Modified Monday, 15-Jul-2002 10:29:24 EDT.