PSTSWM Paragon Serial Performance

Performance Studies using

PSTSWM

Intel Paragon Serial Performance

Date/Person:	January 16, 1998 / P. Worley
Platform:	Intel Paragon XP/S 150 MP at Oak Ridge National Laboratory:
	1024 MP nodes (3 50-MHz iPSC/860 processors per node)
Environment:	Paragon OSF/1 Release 1.0.4 Server 1.4 R1_4_5
	f77/Paragon Paragon Version R5.0.3
Code Version:	6.2
Make Options:	MACH=paragon-mp COMM=mpi PRECISION=8 PERF=n WORKSPACE=5000000
Compilation Options:	if77 -O4 -Mnodepchk -Knoieee -Msafealloc
Number of steps:	T42: 241 or 481
	T85: 49 or 97
Notes:	not using any special math library routines in these experiments

MEASURED TIME PER TIMESTEP (SEC)

Problem	L1	L2	L3	L16
T42	.463	.928	1.39	7.40
T85	2.67	5.31	7.93

MEASURED MFLOP/SEC RATES

Problem	L1	L2	L3	L16
T42	8.92	8.90	8.91	8.92
T85	9.08	9.13	9.17

DISCUSSION

While the MP nodes have three 50 MHz i860 processors (one of which is normally dedicated to interprocessor communication), only one of these was active for these measurements. The bus bandwidth between the processors and node memory prevent the efficient utilization of more than one processor for computation for this code . Typical of many spectral codes (especially those originally developed on vector machines), PSTSWM uses each datum only 1.3 times on the average for each load from memory (as measured by the Cray hardware performance monitor).