Performance Studies using PSTSWM

HP/Convex SPP-2000 SWAP Performance

(ordered swap of 8Kb message using MPI)

ordered simple swap

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 157.61 5.42 57.6% 10 iter. 176.93 5.37 57.4%

ordered swap using nonblocking send

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 123.26 8.23 47.5% 10 iter. 140.75 8.62 45.2% 1 iter. w/overlap 105.64 10.76 41.9% 10 iter. w/overlap 119.68 10.97 36.8%

ordered swap using nonblocking receive

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 116.97 11.76 42.7% 10 iter. 136.08 11.85 42.0% 1 iter. w/overlap 128.09 17.60 43.8% 10 iter. w/overlap 125.73 17.01 31.6%

ordered swap using nonblocking send and receive

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 118.69 11.77 42.4% 10 iter. 137.56 11.74 41.1% 1 iter. w/overlap 112.29 19.58 32.8% 10 iter. w/overlap 125.93 18.82 31.2%

ordered swap using ready send

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 107.12 24.28 32.7% 10 iter. 123.75 25.29 38.2% 1 iter. w/overlap 131.02 17.48 38.3% 10 iter. w/overlap 130.76 16.91 32.6%

ordered swap using nonblocking ready send

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 108.56 25.17 33.4% 10 iter. 125.07 25.47 38.9% 1 iter. w/overlap 113.77 19.39 33.3% 10 iter. w/overlap 126.13 18.83 30.8%

synchronous

Data Statistics unidirectional bandwidth estimated latency model error (peak MByte/sec) (usec/msg) (max. rel. error) 1 iter. 142.57 6.60 56.7% 10 iter. 171.37 6.80 54.6%

DISCUSSION

• Note that these experiments are between processors in the same hypernode. Similar tests across hypernodes would be needed to fully characterize this architecture's point-to-point message-passing performance.
• The experiments using multiple iterations show the effect of the improved memory locality intrinsic to the iteration logic, giving better performance for certain message sizes. This is unlikely to be indicative of performance in real applications.

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Patrick H. Worley / ( worleyph@ornl.gov)
Last Modified Monday, 15-Jul-2002 10:22:51 EDT.
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