PSTSWM POWER4-1.3 Serial Performance

Performance Studies using

PSTSWM

Date/Person:	October 18, 2001 / P. Worley
Platform:	IBM Regatta H system at Oak Ridge National Laboratory (cheetah.ccs.ornl.gov):
	1 16-way Regatta H SMP nodes (1.3 GHz POWER4, 2 8-way Mulitchip Modules)
Environment:	AIX 5.1
Code Version:	6.7.4
Make Options:	MACH=sp COMM=mpi PRECISION=8 PERF=n WORKSPACE=20000000 MATH=essl
Compilation Options:	mpxlf -O3 -qarch=auto -qtune=auto -qcache=auto
Link Options:	-bmaxdata:0x70000000
Number of steps:	T5, T10, T21, T42: 241 or 481
	T85: 49 or 97
	T170: 49 or 97
Number of processors per node:	1, 2, 3, or 4
Notes:	using ESSL library routines for Fourier transforms and BLAS (-lessl)

T5 MFlop rates

Per Processor Rate

Per Node Rate

**T5 MFlop rates**
Per Processor Rate	Per Node Rate

T10 MFlop rates

Per Processor Rate

Per Node Rate

**T10 MFlop rates**
Per Processor Rate	Per Node Rate

T21 MFlop rates

Per Processor Rate

Per Node Rate

**T21 MFlop rates**
Per Processor Rate	Per Node Rate

T42 MFlop rates

Per Processor Rate

Per Node Rate

**T42 MFlop rates**
Per Processor Rate	Per Node Rate

T85 MFlop rates

Per Processor Rate

Per Node Rate

**T85 MFlop rates**
Per Processor Rate	Per Node Rate

T170 MFlop rates

Per Processor Rate

Per Node Rate

**T170 MFlop rates**
Per Processor Rate	Per Node Rate

In this analysis, the experiment computational rates are graphed as a function of the total number of vertical levels on the node. Thus the experiments using more processors have a smaller problem granularity per processor, resulting in improved cache utilization. The total memory required per node is approximately constant for a given number of "node" levels. Therefore the total volume moved between memory and processors for a given number of "node" levels should also be somewhat less for the experiments using more processors, due to the improved cache utilization. However, if the total problem size is large enough to saturate the processor to memory bandwidth, then this bandwidth constrains the cumulative computational rate for the node, and the individual per processor computational rates will suffer.
This experiment indicates an upper bound on the performance one might see when parallelizing a problem across the processors of a node, in as far as it does not include message passing or thread creation or synchronization costs.
Note that two different metrics are displayed - per processor computational rate and per node computational rate. The per node rate is the best measure of the performance of the architecture, but the per processor rate is a convenient way to observe performance degradation.