PSTSWM SP2-66 Serial Performance

Performance Studies using

PSTSWM


IBM SP2-66 Serial Performance

(Using ESSL Math Library)

Date/Person: August 12, 1996 / P. Worley
Platform: IBM SP2 at NASA Ames Research Center (babbage.nas.nasa.gov):
     160 RS6000/590 nodes ("wide", 66.7 MHz POWER2 RISC chip set)
Environment: AIX 4.1.3.3;   POE 2.1.0.8
Code Version: 6.1
Make Options: MACH=sp COMM=mpi PRECISION=8 PERF=n MATH=essl WORKSPACE=5000000
Compilation Options: mpxlf -O3 -qarch=pwr2
Number of steps: T42: 241 or 481
T85: 49 or 97
Notes: using ESSL library routines for Fourier transforms and BLAS

MEASURED TIME PER TIMESTEP (SEC)

Problem L1 L2 L3 L16
T42 .042 .084 .126 .726
T85 .225 .479 .710  

MEASURED MFLOP/SEC RATES

Problem L1 L2 L3 L16
T42 98.3 98.3 98.3 91.0
T85 107.7 101.2 102.4  

Patrick H. Worley / ( worleyph@ornl.gov)
Last Modified Monday, 15-Jul-2002 10:13:50 EDT.
3390 accesses since 1/2/96.