PSTSWM SP2-120 Serial Performance

Performance Studies using

PSTSWM


IBM SP2-120 Serial Performance

Date/Person: August 21, 1998 / P. Worley
Platform: IBM SP2 at Argonne National Laboratory (quad.mcs.anl.gov):
     80 PS2C nodes ("thin", 120 MHz POWER2 Super Chip)
Environment: AIX 4.2.1;   PSSP 2.3
Code Version: 6.3
Make Options: MACH=sp COMM=mpi PRECISION=8 PERF=n WORKSPACE=20000000
Compilation Options: mpxlf -O3 -qarch=pwr2
Number of steps: T42: 241 or 481
T85: 49 or 97
T170: 49 or 97
Notes: using PSTSWM Fortran routines for Fourier transforms and BLAS

MEASURED TIME PER TIMESTEP (SEC)

Problem L1 L2 L3 L16
T42 0.041 0.090 0.137 0.723
T85 0.259 0.518 0.777 4.179
T170 1.518 3.040 4.563  

MEASURED MFLOP/SEC RATES

Problem L1 L2 L3 L16
T42 100.9 91.5 90.7 91.4
T85 93.6 93.6 93.5 92.8
T170 100.8 100.7 100.6  

Patrick H. Worley / ( worleyph@ornl.gov)
Last Modified Monday, 15-Jul-2002 10:13:01 EDT.
3205 accesses since 1/2/96.