PSTSWM SP2-120 Serial Performance

Performance Studies using

PSTSWM

IBM SP2-120 Serial Performance

(Using ESSL Math Library)

Date/Person: August 21, 1998 / P. Worley
Platform: IBM SP2 at Argonne National Laboratory (quad.mcs.anl.gov):
     80 PS2C nodes ("thin", 120 MHz POWER2 Super Chip)
Environment: AIX 4.2.1;   PSSP 2.3
Code Version: 6.3
Make Options: MACH=sp COMM=mpi PRECISION=8 PERF=n MATH=essl WORKSPACE=20000000
Compilation Options: mpxlf -O3 -qarch=pwr2
Number of steps: T42: 241 or 481
T85: 49 or 97
T170: 49 or 97
Notes: using ESSL library routines for Fourier transforms and BLAS

MEASURED TIME PER TIMESTEP (SEC)

Problem L1 L2 L3 L16
T42 0.033 0.075 0.113 0.597
T85 0.221 0.443 0.665 3.580
T170 1.387 2.781 4.175  

MEASURED MFLOP/SEC RATES

Problem L1 L2 L3 L16
T42 125.7 110.8 109.6 110.6
T85 109.8 109.4 109.3 108.3
T170 110.3 110.0 109.9  
Patrick H. Worley / ( worleyph@ornl.gov)
Last Modified Monday, 15-Jul-2002 10:13:01 EDT.
3297 accesses since 1/2/96.