PSTSWM AlphaSC-1000 Serial Performance

Performance Studies using

PSTSWM

Date/Person:	January 4, 2002 / Patrick H. Worley
Platform:	Compaq AlphaServer SC at Pittsburgh Supercomputer Center (lemieux.psd.edu):
	760 ES45 4-way SMP nodes (1 GHz Alpha 21264C with 8MB L2 cache)
Environment:	Compaq Tru64 UNIX V5.1A
	Compaq Fortran Compiler X5.4A-1684-46B5P
Code Version:	6.8.2
Make Options
T5, T10:	MACH=alpha-sc COMM=mpi PRECISION=8 PERF=n WORKSPACE=20000000 MATH=portable
T21, T42, T85, T170:	MACH=alpha-sc COMM=mpi PRECISION=8 PERF=n WORKSPACE=20000000 MATH=cxml
Compilation Options:	f90 -O4 -assume accuracy_sensitive -math_library accurate -align dcommons -align records -arch host -tune host
Number of steps:	T5, T10, T21, T42: 241 or 481
	T85: 49 or 97
	T170: 49 or 97
Number of processors per node:	1, 2, 3, or 4
Notes:	using CXML library routines for Fourier transforms and BLAS

T5 MFlop rates

Per Processor Rate

Per Node Rate

**T5 MFlop rates**
Per Processor Rate	Per Node Rate

T10 MFlop rates

Per Processor Rate

Per Node Rate

**T10 MFlop rates**
Per Processor Rate	Per Node Rate

T21 MFlop rates

Per Processor Rate

Per Node Rate

**T21 MFlop rates**
Per Processor Rate	Per Node Rate

T42 MFlop rates

Per Processor Rate

Per Node Rate

**T42 MFlop rates**
Per Processor Rate	Per Node Rate

T85 MFlop rates

Per Processor Rate

Per Node Rate

**T85 MFlop rates**
Per Processor Rate	Per Node Rate

T170 MFlop rates

Per Processor Rate

Per Node Rate

**T170 MFlop rates**
Per Processor Rate	Per Node Rate

In this analysis, the experiment computational rates are graphed as a function of the total number of vertical levels on the node. Thus the experiments using more processors have a smaller problem granularity per processor, resulting in improved cache utilization. The total memory required per node is approximately constant for a given number of "node" levels. Therefore the total volume moved between memory and processors for a given number of "node" levels should also be somewhat less for the experiments using more processors, due to the improved cache utilization. However, if the total problem size is large enough to saturate the processor to memory bandwidth, then this bandwidth constrains the cumulative computational rate for the node, and the individual per processor computational rates will suffer.
This experiment indicates an upper bound on the performance one might see when parallelizing a problem across the processors of a node, in as far as it does not include message passing or thread creation or synchronization costs.
Note that two different metrics are displayed - per processor computational rate and per node computational rate. The per node rate is the best measure of the performance of the architecture, but the per processor rate is a convenient way to observe performance degradation.