Paragon ATM OC12 tests
Sandia has procured four
ATM OC12 interface boards (ATM OC-12c Protocol Engines from
GigaNet, Inc.) for
This page describes early testing of these interfaces
with GigaNet, Intel, Sandia, and ORNL's Center for
One objective is to interconnect multiple Paragons
over ATM at OC12 speeds
to concurrently work on a single application using
Long term goals include cross-country Paragon ATM interconnects.
Candidate applications include
PCTH, global climate modeling
( CHAMMP ),
GigaNet ATM OC-12c Protocol Engine
is an MP3 I/O node (2 slots) that is
attached to the Paragon mesh.
The GigaNet interface board
supports all appropriate full
duplex STS-12c/OC-12c CCITT physical layer requirements.
The hardware interface has receive and transmit buffers,
SAR logic, TCP/IP acceleration logic, and logic for direct
access to the Paragon mesh.
For further details on the GigaNet interface
"A High Performance ATM Protocol Engine for the Intel Paragon"
(ISUG, Jun '95).
The GigaNet ATM API provides a low level, but high performance
applications interface to the ATM/AAL5 layer.
(Click here for 160K postscript API manual.)
ATM/AAL5 is a connection-oriented best effort packet transfer service.
Packets can be up to 65,536 bytes in length.
The programmer is responsible for providing a queue of receive
buffers, for polling to see if data is available, and for
managing time-outs and re-transmissions.
No operating system services are used by the API, in particular,
the ATM message passing (like NX) is not part of the UNIX I/O paradigm.
The API presently supports only 255 circuits per ATM interface,
though a Paragon may have more than one GigaNet ATM interface.
GigaNet is developing an IP over ATM service based on
Here is the latest (7/16/96) document
describing TCP/IP over the GigaNet ATM.
Principal Investiagtor Tom Pratt, Sandia, email@example.com
Principal Investiagtor Steve Gossage, Sandia, firstname.lastname@example.org
Buddy Bland, ORNL, email@example.com, systems and logistics
Tom Dunigan, ORNL,
David Fair, Intel, firstname.lastname@example.org, Intel SSD rep.
Dave Follett, Giganet, email@example.com, hardware
Maria Gutierrez, Giganet, firstname.lastname@example.org, hardware
Alden Jackson, Sandia/CA, email@example.com, ATM
ORNL, firstname.lastname@example.org, ATM
Peter Molnar, Intel at ORNL, email@example.com, systems
ORNL, firstname.lastname@example.org, PVM
Rich Prohaska, Giganet, email@example.com, software
Tony Ralph, Intel at Sandia, firstname.lastname@example.org, ATM
Allen Robinson, Sandia, email@example.com, applications
Tim Sheehan, ORNL, firstname.lastname@example.org, applications
If you wish to send email to all participants try
- 9/28-29/95, Sandia acceptance tests at Beaverton
- 10/13/95, multi-board and FORE switch tests at GigaNet
- 10/23-27/95, benchmark (NIC A & B),
PVM tests, install XPE, 2 Paragon tests
- 10/30-11/3/95, GigaNet IP tests, Sandia video and
OC3 delay tests
- 11/6-11/95, application tests, IP and video tests, PVM tuning
- 11/27/95, pack & ship XPE, FORE switch, video gear, ATM boards
- 12/4-6/95, SC 95
- 12/95 Sandia to ORNL tests
- 8/96 Sandia/Giganet get R&D 100 Award for OC-12 board
- Beaverton tests 9/28-29/95,
single board acceptance, optics
- GigaNet tests 10/13/95, FORE switch tests
- ORNL tests 10/19-27/95,
one/two service nodes
- ORNL tests 10/30-11/3/95.
two Paragon message-passing tests, OC3 delay tests, IP/ATM tests, PVM,
- ORNL tests 11/6-27/95.
PVM application testing, ATM/IP tests, ATM video tests.
- PCTH results
from SC95, 12/6/95
- bandwidth plot comparing new ATM boards
and libatm.a to earlier results. 3/25/96
- GigaNet/Sandia report 14 MBs TCP and 50 MBs transmit/20 MBs receieve with
UDP between MP nodes over IP/ATM. 5/25/96
- ORNL tech report summarizing 1995 tests, available
``Performance of ATM/OC-12 on the Intel Paragon'',
ORNL/TM-13239, 1996 (253KB)
7/26/96. The LSMS applications is achieving 12.6 MB/s with PVM over ATM,
compared with 200 KBs for Ethernet.
- 8/15/96. Pratt conducts DS3 long-line delay tests.
Molnar's TCP/IP over ATM test results
OC12-to-OC3 packet loss for packets larger than 8K. (Giganet was
setting cell bit so that it cells were candidate for discard, and
FORE has a 256 cell buffer for such low priority cells. Giganet
will change default.)
These 1997 results show NIC-A/B bandwidth
when turned around at an ATM switch. Also shown are effects
of traffic-shaping from the Paragon ATM to match its ATM speeds
with slower wide area links.
Here are August, 1997 VCI info and
Chuck Fisher's circuit maps for ORNL
Here are 11/16/95
ATM/PVC switch configurations
and the current configurations of
the two Paragons.
Last Modified by
back to Tom Dunigan's page
or the ORNL home page