Table of Contents
MFIX Parallelization
Parallelization Team
Objective
Serial Code Enhancements
Parallelization Strategy
Parallelization Strategy (continued)
Parallelization Effort
Test Cases for Parallel Code Verification
Test Problem
Computer Platforms
Computer Platforms (continued)
Computer Platforms (continued)
Timing under IBM SP (ORNL)
PPT Slide
Timing under IBM SP (NERSC)
PPT Slide
Timing under Compaq
PPT Slide
Timing under Beowulf
PPT Slide
PPT Slide
PPT Slide
Concluding Remarks
Future Plans
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Author: Sreekanth Pannala and Eduardo D'Azevedo
Email: pannalas@ornl.gov
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